Illegal range in part select

SystemVerilog
1

I’m not sure how to resolve this error.

The testbench defines:
parameter integer ABC = 321616;

The block that uses this is instantiated:
.ab_adr_i (ab_mem_adr_i[my_width(CONFIG.ABC)-1:0]),
But the error indicates it’s illegal and doesn’t acknowledge the parameter.
The range of the part select is illegal:
wb_mem_adr_i[-1:0]

What is missing?

2

In reply to deadspace:

It would help to show the decorations of everything used in the line that has the problem.

What is CONFIG? What is my_width? Is ab and wb typos?