Illegal expression within the binsof construct

SystemVerilog
, ,
1

I’m trying to create a cross coverage for coverpoint osc_freq using the code shown below:

  
   chanl_length : coverpoint cfg.chanl_length {
       bins ch16 = {'d16};
       bins ch32 = {'d32};
     }

     no_of_channels : coverpoint cfg.no_of_channels {
       bins t2 = {'d2};
       bins t4 = {'d4};
       bins t8 = {'d8};
     }

    osc_freq : cross cfg.chanl_length,cfg.no_of_channels {
       bins f1p536 = binsof(no_of_channels.t2) && binsof(chanl_length.ch16); 
       bins f3p072 = binsof(no_of_channels.t2) && binsof(chanl_length.ch32)   ;
      }

However, the compiler is showing “Illegal expression within the binsof construct” error and it is pointing towards “no_of_channels.t2” and “chanl_length.ch16” part of the code. Isn’t this snippet syntactically correct, can someone point out the error?

2

In reply to ambreezesj:

Your problem is you need to cross the two coverpoint labels your declared, not the original expressions.

    osc_freq : cross chanl_length, no_of_channels {