I'm trying to write a SVA for the following scenario :
I want to ignore the value of a signal 'a' for the the first 36 cycles and after that if signal 'a' goes high, signal 'b' should go high in the same cycle.
The signal 'a' which could potentially glitch for about 36 clocks and hence want to ignore it.
I couldn't construct a reliable assertion model but I attempted to do this in the following way :
disable iff (!rstb)
@(posedge clk) 1 |-> ##36 1 |-> ##[0:$] a |-> b;
endproperty : p_glitch
a_glitch : assert property(p_glitch);
Immediately there were several problems with this.
1. The signal 'a' could potentially never happen as per the design which is okay. I want to check signal 'b' going high only if 'a' goes high. In my above assertion, I expect my assertion to fail if 'a' never toggles.
2. Even when the signal 'a' toggles, the assertion is always in active state (never finishes)
Can you please explain what is going on with the above assertion and how to effectively write this?
Thanks in advance.