If timeunit and timeprecision declaration is mandatory with a value which is power of 10 units?

SystemVerilog
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1

SV LRM says that,
*Section 18.10: Time unit and precision
Use of these declarations removes the file order dependencies problems
with compiler directives. The time unit and precision can be declared by the timeunit and
timeprecision keywords, respectively, and set to a time literal which must be a power of 10 units.
*

Does this mean, I can’t write as below?


timeunit 1ns; 
timeprecision 1fs;

If it is not allowed, how can I have precision of 1fs in my environment?

2

In reply to psubudhi:

10 to the power 0 is 1.

3

In reply to dave_59:

In reply to psubudhi:
10 to the power 0 is 1.

Thanks.