If there are two or more 'solve before' in the constraint, which one would be first served?

SystemVerilog
,
1

Hello, Here is a constraint with two ‘solve before’ and I have little idea which one would be first to served in the solution.


    class my_test extends uvm_object;
      rand bit a;
      rand bit[31:0] b;
      rand int unsigned c, d;

      constraint my_cons {
        a -> b == 0;
        solve a before b;

        c inside {[0:1]};
        d inside {[0:10]};
        c * d == 0;
        solve c before d;

        b == c;
      }
    endclass

    my_test t;

One simulator output
num_a = 235 (1/4)
num_c = 510 (1/2)

while another simulation output
num_a = 387 (3/8)
num_c = 385 (3/8)


    repeat(1000) begin
        t.randomize();
        num_a += t.a ? 1 : 0;
        num_c += t.c ? 1 : 0;
    end
    $display("num_a = %0d", num_a);
    $display("num_c = %0d", num_c);

Please kindly give me some background of ‘solve before’ knowledge on this. Thank you

2

In reply to zz8318:

This is loosely described in section 18.5.10 Variable ordering. Basically it says tools will do their best to get the proper distributions, but there are no guarantees.

3

In reply to dave_59:

Yes, I see. But it still confused me that why the result is difference if we use different tool with the same code.

4

In reply to zz8318:

Vendors make tradeoffs between performance and getting perfectly balanced results. Since this Mentor sponsored public forum is not for discussing tool specific issues, you’ll have to take that up with your tool vendor.

5

In reply to dave_59:

got it . Thank you