If i replace automatic with static i will get output, why it shows error if i write automatic instead of static in below example

SystemVerilog
1 
module factorial;
  task automatic factorial(
    int numb=5,
    integer fact=1);
    for(int j=numb;j>0;j--)
      fact*=j;
   $monitor("output %d",fact);
  endtask
  initial begin
    factorial();
  end
endmodule
2

In reply to swapnilsrf9:

Your code works with both static and automatic qualifier. Might be a tool issue.

3

In reply to swapnilsrf9:

If you are getting an error message, it always helps to show the actual error saving people’s time you want a response from.

The error message I’m getting says “Automatic variables not allowed as arguments to $monitor”. The reason for this is explained in section 6.21 Scope and lifetime of the 1800-2012 LRM. You can only use automatic variables in a procedural context, and $monitor is a task that executes outside of that context. The Verilog LRM explicitly list $monitor as being illegal, but somehow the explicit list of non-procedural constructs was dropped when they merged the Verilog and SysyemVerilog LRMs. See 0001967: Restrictions on automatic and dynamic variables are incomplete - Accellera Mantis

In any case, $monitor is not a very useful construct because you are only allowed one active $monitor at a time, and it only displays values at the end of the time slot.