If condition with array

SystemVerilog
, ,
1 
bit [6:0] a;
integer b;
bit[7:0] c;

a=5;

if(c%a[b]==o) begin
  true
end

here c values varies from 0 to 5 and b value from 0 to 52 at what situations the if condition will be satisfied and how???

2

In reply to kartick:

a is a packed array of 7 bits, a[b] is one-bit width with value of either 1’b0 or 1’b1.
when a[b] equal to 1’b1, the c%a[b] result is equal to 0.
when a[b] equal to 1’b0, the c%a[b] result is equal to x.

So when a=5, b=0 or b=2 will have c%a[b]==0 condition to be true. c can be any value.

3

In reply to Lina.Lin:

In reply to kartick:
a is a packed array of 7 bits, a[b] is one-bit width with value of either 1’b0 or 1’b1.
when a[b] equal to 1’b1, the c%a[b] result is equal to 0.
when a[b] equal to 1’b0, the c%a[b] result is equal to x.
So when a=5, b=0 or b=2 will have c%a[b]==0 condition to be true. c can be any value.

but this condition gets passed in other b values also like 11 41 how is it possible when i tried the same with c value as 10 it gets passed at b = 1,3,11,12, please explain this

4

In reply to kartick:

I suggest you to debug your code with message print of all the variables and c%a[b] value as below.

`uvm_info(get_type_name(), $psprintf("a=%0d, c=%0d, b=%0d, a[b]=%0d c%%a[b]=%0d",a, c, b,  a[b], c%a[b]), UVM_NONE)
5

In reply to kartick:

Please read http://sscce.org/ to increase the chance of someone understanding and answering your question.