I want to write an assertion where genclock must rise in the setup or hold time window(say 2ns each) of refclock. Is there a in built timing check for this?
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In reply to soh2415:
Hey, so generally speaking SVA are not intended to be used to check timing, I’d recommend using the Systemverilog timing system task like $setup $hold $width and $period.
My suggestion is to create a module called timing check and encapsulate those tasks into a specify endspecify. All those tasks, mainly setup and hold (which i believe are the ones you should be using) provide and output called notifier. You can use this bit to check if the timing constraint has been violated.
In reply to Rsignori92:
Can you specify a code. I have gone through timing checks but not getting clarity
In reply to soh2415:
Here is an example that you can use as a guideline:
module top2(output logic clk, d);
`include "uvm_macros.svh"
import uvm_pkg::*;
timeunit 1ns; timeprecision 100ps;
logic a, d1;
bit[1:0] delay;
realtime duration= 2.0ns;
initial begin
clk=0;
forever #5 clk = !clk;
end
always @(posedge clk) begin
if (!randomize(a, delay) with {
delay dist {2'b01 := 1, 2'b11 := 1};
}) `uvm_error("MYERR", "This is a randomize error");
#delay d<=a;
end
property hold_chk;
realtime clock_sample;
@(posedge clk)
(1,clock_sample = $realtime)##0 (1,$display("clock_sample=%0t",clock_sample)) |->
@(d)((1,$display("data_sample=%0t,difference=%0t",$realtime,$realtime-clock_sample))##0
($realtime - clock_sample) >= duration);
endproperty : hold_chk
HOLD_CHK : assert property (hold_chk)
// $display("****ASSERTION_PASSED**** clock");
else
$display ("%0t ERROR Hold****",$realtime);
property setup_chk;
realtime clock_sample;
@(d)
(1,clock_sample = $realtime)##0 (1,$display("d_sample=%0t",clock_sample)) |->
@(posedge clk)((1,$display("clk_sample=%0t,difference=%0t",$realtime,$realtime-clock_sample))##0
($realtime - clock_sample) >= duration);
endproperty : setup_chk
SETUP_CHK : assert property (setup_chk)
// $display("****ASSERTION_PASSED**** clock");
else
$display ("%0t ERROR setup****",$realtime);
setup_time_check setup_time_check1(clk, d);
initial #2000 $finish;
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…
- SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
- Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
Real Chip Design and Verification Using Verilog and VHDL($3) Amazon.com - Papers:
- Understanding the SVA Engine,
Verification Horizons - July 2020 | Verification Academy - SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
https://www.udemy.com/course/sva-basic/
https://www.udemy.com/course/sv-pre-uvm/
In reply to ben@SystemVerilog.us:
Wrong model, here is another one:
module top();
timeunit 1ns; timeprecision 100ps;
`include "uvm_macros.svh"
import uvm_pkg::*;
logic a, clk=0;
bit[1:0] delay;
realtime duration=2ns;
initial forever #5 clk = !clk;
always @(posedge clk) begin
if (!randomize(a, delay) with {
delay dist {2'b01 := 1, 2'b11 := 1};
}) `uvm_error("MYERR", "This is a randomize error");
end
assign #delay d = a;
specify
//$setuphold(posedge clk, d, -1, 2);
endspecify
property hold_chk;
realtime clock_sample;
@(posedge clk)
(1,clock_sample = $realtime) |-> @(d) ($realtime - clock_sample) >= duration;
endproperty : hold_chk
HOLD_CHK : assert property (hold_chk)
$display("****ASSERTION_PASSED");
else
$display ("%0tERROR****The value of d is %b",$realtime, $sampled(d));
property hold_chk1;
realtime clock_sample;
@(posedge clk) (1,clock_sample = $realtime) |->
@(d) ($realtime - clock_sample) >= duration;
endproperty : hold_chk1
HOLD_CHK1 : assert property (hold_chk1);
setup_time_check setup_time_check1(clk, d);
initial #2000 $finish;
endmodule
module setup_time_check(input clk, data);
timeunit 1ns; timeprecision 100ps;
let tSU=2ns;
let tHLD=2ns;
bit notifier1;
specify
$width(posedge clk,5);
$period(posedge clk,10);
/* $setuphold ( reference_event , data_event , timing_check_limit , timing_check_limit
[ , [ notifier ] [ , [ timestamp_condition ] [ , [ timecheck_condition ]
[ , [ delayed_reference ] [ , [ delayed_data ] ] ] ] ] ] ) ; */
$setuphold( posedge clk, data, tSU, tHLD, notifier1 );
endspecify
endmodule
module top2(output logic clk, d);
`include "uvm_macros.svh"
import uvm_pkg::*;
timeunit 1ns; timeprecision 100ps;
logic a, d1;
bit[1:0] delay;
realtime duration= 2.0ns;
initial begin
clk=0;
forever #5 clk = !clk;
end
always @(posedge clk)
begin
if(randomize(a, delay));
#delay d<=a;
end
property hold_chk;
realtime clock_sample;
@(posedge clk)
(1,clock_sample = $realtime)##0 (1,$display("clock_sample=%0t",clock_sample)) |->
@(d)((1,$display("data_sample=%0t,difference=%0t",$realtime,$realtime-clock_sample))##0
($realtime - clock_sample) >= duration ) ;
endproperty : hold_chk
HOLD_CHK : assert property (hold_chk)
$display("****ASSERTION_PASSED**** clock");
else
$display ("%0tERROR****",$realtime);
setup_time_check setup_time_check1(clk, d);
initial #2000 $finish;
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…
- SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
- Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
Real Chip Design and Verification Using Verilog and VHDL($3) Amazon.com - Papers:
- Understanding the SVA Engine,
Verification Horizons - July 2020 | Verification Academy - SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
https://www.udemy.com/course/sva-basic/
https://www.udemy.com/course/sv-pre-uvm/
In reply to Rsignori92:
Include this in your module. This checks for the violations.
specify
$setup(gen_clk, posedge ref_clk, 2);
$hold(posedge ref_clk, gen_clk, 2);
endspecify