I couldn't understand how display and monitor are working in initial block, how j =10 is coming as it would not be able to go in to loop when i =10?

SystemVerilog
1

module tb;
int i;
initial begin

for(i = 0; i<10; i++)
begin 
  $display("i = %d",i);
end
for(i=0; i <10; i++)

begin 
  $monitor("j = %d",i);
end

end
endmodule

simulation log:
Compiler version Q-2020.03-SP1-1; Runtime version Q-2020.03-SP1-1; Jul 19 08:25 2021
i = 0
i = 1
i = 2
i = 3
i = 4
i = 5
i = 6
i = 7
i = 8
i = 9
j = 10

2

In reply to ejaz_parvez:

For loops are 0 delay loops so they do not consume time or simulation steps. The monitor task is executed at the end of the time steps not in active region.

So your first loop will execute in active region (where display are executed) but the monitor is executed only at the really end where the loop itself is completely finished. So you see only the last one (10).

3

In reply to Rsignori92:

When i becomes 10 after the first for loop, how the monitor statement is getting executed even when it is not satisfying the for loop condition?

4

In reply to neha_kashyap:

You have 2 for loops and in both you init i to 0. The loop condition cames after