Hi all,
I’ve created a uvm sv file (it is actually a register block), which has the following format:
class X extends uvm_reg_block;
rand reg1 x1[255];
rand reg2 x2[255];
rand reg3 x3[255];
// and so on - thousands of registers (reg1,reg2,reg3 are rand classes).
constraint reg1_0_const {…};
constraint reg1_1_const {…};
constraint reg1_2_const {…};
…
constraint reg2_0_const {…};
constraint reg2_1_const {…};
constraint reg2_2_const {…};
…
constraint reg3_0_const {…};
constraint reg3_1_const {…};
constraint reg3_2_const {…};
…
endclass
Since I have a huge number of registers, and each register has several corresponding constraints (regarding each of its fields), the sum of the constraints is enormous (>50K). when I try running a test with the following configuration, I get a vcs error which states “vcs Error-[NONMEM] Out of memory” (after getting “starting vcs inline pass”). I tried running with a 64 bit flag, but the problem remains. when I clear the constraint code (the main “X” class remains, but the constraints logic is omitted) the problem vanishes.
Is there a way to avoid this issue?
I don’t really know why the problem occurs :
- Is it just since the class has too many lines of code in it? if so, maybe splitting it to smaller classes and instantiating them in a higher level class would help?
- Will splitting the class into several hierarchies and using inheritance might solve the problem?
I’d appreciate any idea.
Thanks,
Eyal.