I want to model a controller where after one read to another read there should be 3 clk cycles delay. From read to write 6 clk delays. How to introduce these delays!
How to write a Verilog or SV code to model this delay btw read and read signal in memory controller?
In reply to Sv-hustler:
Model is for read-to-read and write-to-write. Modify as needed.
Use automatic tasks with the fork join_none. See my paper SVA in a UVM Class-based Environment (link in my signature below).
bit clk, rd, rd_cntlr, wr, wr_cntlr;
task automatic rd4cntlr(int delay, bit value);
repeat(delay-1'b1) @(posedge clk);
rd_cntlr <= value;
endtask //automatic
task automatic wr4cntlr(int delay, bit value);
repeat(delay-1'b1) @(posedge clk);
wr_cntlr <= value;
endtask //automatic
always_ff @(posedge clk) begin
fork
rd4cntlr(3, rd);
wr4cntlr(6, wr);
join_none
end
testbench
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
bit clk, rd, rd_cntlr, wr, wr_cntlr;
default clocking @(posedge clk);
endclocking
initial forever #10 clk=!clk;
task automatic rd4cntlr(int delay, bit value);
repeat(delay-1'b1) @(posedge clk);
rd_cntlr <= value;
endtask //automatic
task automatic wr4cntlr(int delay, bit value);
repeat(delay-1'b1) @(posedge clk);
wr_cntlr <= value;
endtask //automatic
always_ff @(posedge clk) begin
fork
rd4cntlr(3, rd);
wr4cntlr(6, wr);
join_none
end
ap_rd1: assert property(@ (posedge clk) rd |-> ##3 rd_cntlr);
ap_rd0: assert property(@ (posedge clk) !rd |-> ##3 !rd_cntlr);
ap_wr1: assert property(@ (posedge clk) wr |-> ##6 wr_cntlr);
ap_wr0: assert property(@ (posedge clk) !wr |-> ##6 !wr_cntlr);
initial begin
repeat(200) begin
@(posedge clk); #1;
if (!randomize(rd, wr) with
{ rd dist {1'b1:=1, 1'b0:=3};
wr dist {1'b1:=1, 1'b0:=4};
}) `uvm_error("MYERR", "This is a randomize error")
end
$finish;
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA: Package for dynamic and range delays and repeats | Verification Academy
- SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy