How to write verificaiton environment for memory / register bank

I’ve recently learned about verification environment creation with systemverilog: (I’m still putting everything together)

Send data in DUT with driver and to scoreboard through mailbox
DUT does the processing
Collect processed data with monitor and send to scoreboard through mailbox
Scoreboard has actual values and it computes expected values to compare against each other to verify the result

However how about if design has a register bank / banks (if there are multiple banks then each have different address). In that case according to address the data changes (it is not simple data stream). How does above steps work in this case?