How to write a union data structure in systemverilog

In c/c++ language, I use below code to implement a union data structure. But I have little idea how to do the same thing in SystemVerilog. It always reported : Unpacked unions are not yet supported.

typedef union {
    struct {
    	int unsigned               offset : 25;
    	int unsigned               id : 7;
    } f;
    int unsigned dataAll;
} my_dw;

Thank you for any help.

In reply to zz8318:

“not yet supported” means your tool recognizes the construct, but has not implemented it yet. Also, SystemVerilog does not have struct bit-fields.

What you want is a packed struct, not a union.

typedef struct packed {
 bit [24:0] offset;
 bit [6:0] id;
} my_dw;

my_dw data;

Then you can refer to data, or data.id, data.offset. (data by itself would be the whole thing)

In reply to dave_59:

Thank you very much. I got it.