How to write system verilog assertion for I2C

SystemVerilog
1

Hi All,
I want to write an assertion for i2c where sda data should be stable for each positive edge of scl. I am unable to figure out that how to write this assertion. please help me on same.

Thanks & Regards,
Arpan Jasdhav,
verification engineer I,
Mindlance Technology, Bangalore

2

In reply to Arpan Jadhav:

Hi arpan,
You should declare some flags in interface to indicate when the transfer is a command or data.Based on that use @sda as clocking event and check that scl is low at that time and also disable this assertion when the command signal flag (start or stop)is high.

3

In reply to rajanpassionate:
Hi rajanpassionate,
i have already took start and stop condition flag in interface based on @sda which indicated start and stop condition for sda bus but i want check data validity for sda as mention is specification -
“The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is
LOW”

4

In reply to Arpan Jadhav:



Arpan,
You can try writing the property this way.This worked for me.(Provided you should assert the respective flags at the right instant)
property p3;
@(I2C_INTERFACE.sda) disable iff(!I2C_INTERFACE.scl || I2C_INTERFACE.start || I2C_INTERFACE.stop ||  I2C_INTERFACE.idle) (I2C_INTERFACE.scl==1'b1) ;
endproperty
5

In reply to Arpan Jadhav:

In reply to rajanpassionate:
Hi rajanpassionate,
i have already took start and stop condition flag in interface based on @sda which indicated start and stop condition for sda bus but i want check data validity for sda as mention is specification -
“The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is
LOW”

Looks to me that this is not a SVA type of check because what you are looking is a continuous (not clocked) test where as long as clk==0 past_sda = sda // store value in a latch.
Then when clk==1 sda should not change (i.e., sda==past_sda), else an err signal is true.
always @(posedge err) $display(" %t sda error", $time); will flash the error condition.


module top; 
    bit clk, a, b; 
    logic err_n, sda, past_sda; 
    initial forever #10 clk=!clk;  
    always_latch if(!clk) past_sda = sda; 
    assign err_n= clk ? sda==past_sda : 1'b1; 
  always @(negedge err_n) $display(" %t sda error", $time); 
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

6

In reply to ben@SystemVerilog.us:
Thanks,Ben Cohen

7

In reply to Arpan Jadhav:


property sda_stable_while_scl_high;
@(posedge high_freq_clk)
$rose(scl) |-> (sda && scl == 1) || (!sda && scl == 1) throughout !(scl[->1]); //Idea is to catch glitch in sda while scl high
endproperty

p_assert : assert property (sda_stable_while_scl_high)

Suggestions are welcome. Can this be modified or can we use throughout operator in this type of assertions