How to write SV checker for verifying if a DUT produced right image

SystemVerilog
1

Suppose a DUT is producing image as below.

9x9 image with each pixel can be a enumerated value (typedef enum {on,off,random} pixel_t}.

  1. the number of off has to be less than 10%.
  2. The 3x3 array’s internal to 9x9 image should not have all off pixels.

I understand how to write constraints to generate this image, but how to verify if DUT is producing the image corectly?

Any idea/hints/suggestion?

2

In reply to n347:

Since the image is generated using an algorithm imposed on the input data, isn’t the comparison of the generated DUT image with an image generated by simulation of the algorithm sufficient?

If you are talking about a randomly generated image, you can impose that image against a reference model that creates the expected results.
If you only want to check that the statistics on the quality of the image produced (the items 1 and 2 in your list), then a simple count of the types of pixels produced should be sufficient. Of course, that does not guarantee that the filtering requirements are met.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
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  1. SVA Alternative for Complex Assertions
    Verification Horizons - March 2018 Issue | Verification Academy
  2. SVA: Package for dynamic and range delays and repeats | Verification Academy
  3. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
  4. FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
3

In reply to n347:

If you already understand how to write the constraint expression, then you already know how to write the checker expression—they are both the same thing. You can even call randomize(null) which checks the constraints using the current values of all your variables.

4

In reply to dave_59:

Thanks Dave! I think i have a methodology question.

Monitor will get the DUT output image and can send it to scoreboard, Should the check be in the scoreboard?

pixel_t image[9][9] → output of the DUT

But in the scoreboard how can it check for the number of pixels to be in the below constraints below:

  1. The number of off has to be less than 10%. (if (image.sum < 8) good, else error?)
  2. The 3x3 array’s internal to 9x9 image should not have all off pixels.
    (how to do this, may be grab the image3x3[7][7][3][3] and do the checks? )

reference model can generate the output image as well and scoreboard can compare them…

5

In reply to ben@SystemVerilog.us:

Thanks Ben!
I looked at your paper , Do you think i can consider such assertions in my testbench?

The model holds an image in a 25x25 matrix array.
Each pixel in that image is an unsigned integer. The image is partitioned into 25 slices or
quadrants, and the scoreboard needs to compute within a 5x5 slice the number of pixels
greater than 3. The image is loaded when done_image is true, and the slice to be selected
is determined at a new ld signal. The done_image occurs within 1 to 3 cycles after the ld
signal.

How can i achieve this?
If you are talking about a randomly generated image, you can impose that image against a reference model that creates the expected results.

6

In reply to n347:

Do you think I can consider such assertions in my testbench?

There is a saying that ALL ROADS LEAD TO ROME.

  • The word “assertion” is only a testimony that a property (or something) is true.
  • The techniques in specifying an assertion in SystemVerilog include SVA and plain SystemVerilog code.
  • SVA is constrained to be in modules, checkers, or interfaces.
  • In my paper SVA Alternative for Complex Assertions I demonstrate a technique to emulate SVA anywhere in the design environment, including classes.
    https://verificationacademy.com/news/verification-horizons-march-2018-issue
  • In the next 2020 issue of the Verification Horizons I believe that my next paper Understanding the SVA Engine Using fork-join Model will be published.

In any case, the point that I am making is that if your verification environment is in a class, then use SVA model emulation using tasks. The paper http://systemverilog.us/papers/sva4scoreboarding.pdf demonstrates how SVA is used to trigger the needed functions to do complex computations and verification. But in the end, it all boils down to the same thing. It’s interesting that my model has a lot of similarities to your requirements.
Thus, yes, you can use a similar approach for your verification.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

  1. SVA Alternative for Complex Assertions
    https://verificationacademy.com/news/verification-horizons-march-2018-issue
  2. SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  3. SVA in a UVM Class-based Environment
    https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
7

In reply to n347:
The sum constraint expression can be used directly as an assertion

assert ( pixel_t image.sum(D1) with (D1.sum(D2) with (int'(D2==OFF)) ) < 8);

This is what I meant by using a procedural for-loop in my other post

pass == 1;
for (int i=1;i<9 && pass;i++)
  for (int j=1;j<9 && pass;j++) begin
     int count = 0;
     for(int g=i-1;g<=i+1;g++)
       for(int h=j-1;h<=j+1;h++)
          count += pixel_t image[g][h] == OFF;
     if (count == 9) pass = 10;
  end
assert (pass);