How to write multiple conditions with SystemVerilog Assertions

Hi All,

My requirement is to toggle a signal named X from 0 to 1 and 1 to 0.
And to do that i need to configure a register R to 1 to make X 0 to 1 and R to 2 (any value apart from 1) to make X 1 to 0.

below is what i have tried but not sure if i’m following proper sysntax

example1 :

assert_R_X : assert property
(@(posedge clk) disable iff (rst)
((state) && (rdy) && (R==1) |=> (X==1))
else if (state) && (rdy) && (R==2) |=> (X==0));

example2 :

sequence r_1_x_1;
((state) && (rdy) && (R==1));
endsequence

sequence r_2_x_0;
((state) && (rdy) && (R==2));
endsequence

assert_R_X : assert property
(@(posedge clk) disable iff (rst)
if (r_1_x_1) |=> (X==1);
else if (r_2_x_0) |=> (X==1));

In reply to Shiv Kamlekarr:

You are not following the syntax of a property statement

 
 property_statement ::=  
   property_expr ;  
 | case ( expression_or_dist ) property_case_item              { property_case_item }   
   endcase  
 | if ( expression_or_dist ) property_expr  [ else property_expr ] 
 
// example 
  case (cntrl)   
    2'd0 : a |=> c;     
    2'd1 : a ##2 b;   
    2'd2 : a ##1 b |-> c;      
    default: 0;   
  endcase 

  if ($rose(ready)) (req) |=> ack else ##1 idle; 

Reevaluate your property statements

Ben systemverilog.us