How to write ignore bins in cross coverage

SystemVerilog
1

I want to cross three coverpoints, each coverpoint is written for a three different single bit variables.
var1 var2 var3
0 0 0
0 0 1
0 1 0 -->ignore
0 1 1 -->ignore
1 0 0
1 0 1
1 1 X

In the above combinations, i need to ignore {0,1,0} and {0,1,1}, and if var1=1 and var2=1, var3 is dontcare.
cp_var1: coverpoint var1;
cp_var2: coverpoint var2;
cp_var3: coverpoint var3;
cp_cross_var1_var2_var3:cross cp_var1,cp_var2,cp_var3 {
ignore_bins ignore = binsof(cp_var1) intersect{0} &&
binsof(cp_var2) intersect {1};}

This is my code which is giving 8 bins, i need to ignore those two bins, Please suggest me to meet my requirement.

2

In reply to kirankumarreddy:

Sometimes it’s easier to concatenate your bits together rather than trying to deal with complex cross expressions

cp_cross: coverpoint {var1,var2,var3} {
 bins included[]    = {[3'b000:3'b111]};
 ignore_bins excluded = {3'b010, 3'b011}; // removes from included bins
}