How to write a checker for req/ack without using assertion

How to write a checker in systemverilog/UVM without assertions to check every req get’s an ack after 10 clock cycles, there can be second or third req when the first req is still waiting for an ack. How can we handle multiple requests?

In reply to poojitha.ch:
I address that topic in my paper

1.1.1 Attempt Uniqueness
Every request has its own grant. This requirement assures that each successful attempted
assertion from start to completion is unique; this means that if multiple assertions are active
waiting for a matched consequent then a successful consequent should not satisfy all those
active assertions.

If you do not want to use SVA, maybe because your code is in a class where concurrent assertions are illegal, you can then use tasks. I explain this use in my paper:


Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
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