How to write bins in system verilog?

SystemVerilog
1

I’m trying to write bins I have the something which I tried. Here, addr is of 8 bits and data is of 1 bit

assign addr= addr[7:0] == 'h75| addr[7:0] == 'h60 | addr[7:0] == 'h58;
covergroup adress @(posedge clk);
verify : coverpoint (data, addr,){
bins data1= {2’b11) ;
}

Is this the correct way of writing? because addr is of 8 bits when we searching for the address is it correct to write as I mentioned above or do we consider as 8 bits?

Note please don’t consider any syntax errors. I just wanted to know how to write bins in the above case

2

In reply to perkin:

Before writing any bins, you need to explain exactly what it is you need to cover. Try explaining it in terms of how many samples you would need to get 100% coverage.