How to write the below posted assertion in proper syntax?

SystemVerilog
, ,
1

hello everyone ,

sequence s3;
  int cnt[int];
    @( posedge aclk)
   (awvalid ) ##0 (awid_arry2[awid] = awlen+1) ##0 (wvalid) ##0 (awid_arry2.exists(wid),cnt[wid]++) ##0 ( cnt[wid] == awid_arry2[awid] ) ##0 (wlast);
  endsequence
   Master_send_awlen_is_equal_times_of_slave_received_data : assert property(s3);

asser, “(awid_arry2[awid] = (awlen + 1))”
Expressions with side effects not allowed in temporal expressions.
Expression: (awid_arry2[awid] = (awlen + 1))

Error-[SFNATE] System functions not allowed here
assertion.sv, 93
asser, “awid_arry2.exists(wid)”
System function ‘exists’ is not allowed in temporal expressions.
Please review the expression and replace the system function within this
context.

Error-[ETTNATE] Invalid type in temporal expression
assertion.sv, 96
cnt[wid] += 1;
, “cnt”
Expressions involving real, string, event, tagged union and dynamic
SystemVerilog types are not allowed in Boolean expressions in properties and
sequences.

3 errors
CPU time: .158 seconds to compile
Exit code expected: 0, received: 1
Done
why this type of errors are generated?
and how to write assertion in proper syntax?
plz check it Edit code - EDA Playground

2

In reply to prashu:

I suggest that you first write your requirements in English.
Then, since your check doesn’t occur over a sequence of clocks, but at every clock, write your assertion in an always block with automatic variables in your block.
Ben Ben@systemverilog.us