How to write assertions for genric clock divider

SystemVerilog
1

Can anyone explains logic for assertions for generic clock divider

2

Can anyone explains logic for assertions for generic clock divider

You need to draw a timing diagram, and then derive assertions based on current conditions. Thus, if “a” is a divide by 2, and b is a divide by 4, then

default clocking cb_clk @ (posedge clk); endclocking 
    ap_a: assert property (a |=> !a); 
    ap_b2hi:     assert property (!a && !b |=> $rose(b)); 
    ap_bstayshi: assert property (a && b   |=> $stable(b)); 
    ap_b2lo:     assert property (!a && b  |=> $fall(b));
    ap_bstayslo: assert property (a && !b  |=> $stable(b));

Ben Cohen http://www.systemverilog.us/

  • SystemVerilog Assertions Handbook, 3rd Edition, 2013
  • A Pragmatic Approach to VMM Adoption
  • Using PSL/SUGAR … 2nd Edition
  • Real Chip Design and Verification
  • Cmpt Design by Example
  • VHDL book
3

In reply to ben@SystemVerilog.us:

Hi Ben,

I have a input clock say inp_clk and output clock say out_clk, the out_clk is a divider clock that is based on the value n, the value n changes all the times .
So,my requirement is to write an assertion such that whenever there is a change in the value n the out_clk should be generated accordingly otherwise report an error.

Can this achieved by using SVA ??

Please , give me your inputs to solve the same.

Thanks,
durga