Search form

Main menu

My Account Menu

How to write assertions for genric clock divider

pmehro
pmehro
Full Access
22 posts

Can anyone explains logic for assertions for generic clock divider

Answers

ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
80 posts

Quote:
Can anyone explains logic for assertions for generic clock divider

You need to draw a timing diagram, and then derive assertions based on current conditions. Thus, if "a" is a divide by 2, and b is a divide by 4, then
 default clocking cb_clk @ (posedge clk); endclocking 
    ap_a: assert property (a |=> !a); 
    ap_b2hi:     assert property (!a && !b |=> $rose(b)); 
    ap_bstayshi: assert property (a && b   |=> $stable(b)); 
    ap_b2lo:     assert property (!a && b  |=> $fall(b));
    ap_bstayslo: assert property (a && !b  |=> $stable(b)); 

Ben Cohen http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, 3rd Edition, 2013
* A Pragmatic Approach to VMM Adoption
* Using PSL/SUGAR ... 2nd Edition
* Real Chip Design and Verification
* Cmpt Design by Example
* VHDL book