How to write assertion with local variables

SystemVerilog
,
1

There are two questions I don’t know that both need local variable.

  1. a will be high for 1clk, then 10 clk later b will high for 1clk.
    But the tricky part is A can rise for several times. Then I need to check each a matches the right b.
  2. a will be always high until seeing b is high, then next clk both will be deasserted. Same thing, I think I need to add local variables to count a and b and check at the end if total are the same.
    But I never write before. Could anyone help on these two questions?
2

In reply to aaaaaa:

There are two questions I don’t know that both need local variable.

  1. a will be high for 1clk, then 10 clk later b will high for 1clk.
    But the tricky part is A can rise for several times. Then I need to check each a matches the right b.

see

  1. a will be always high until seeing b is high, then next clk both will be deasserted. Same thing, I think I need to add local variables to count a and b and check at the end if total are the same.
    But I never write before. Could anyone help on these two questions?

No need for local variables

 
first_match($rose(a) ##1 a[*1:$] ##1 b) |-> 
       ##1 !a && !b;

Ben Cohen
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