- we have clk1, clk2 & clk3 . clk1 and clk2 are the inputs to clk3. have to track the period of clk3 based on req and also need to check the glitch on the clk3.
- clk1 =500MHz ,clk2=400Mhz
- if req=0, clk3 will take clk1 and if req=1 , clk3 will take clk1 after 4 clk cycle delay of clk3.
- how to write the assertion to check the period of clk3.
In reply to vkandhare36@gmail.com:
So clk2 is not used; why even mentioed it in the requirements? Error?
Draw a timing diagram, the requirements are ambiguous.
Ben systemverilog.us