How to write assertion for the case where a signal must be stable for Xns before the assertion of another signal

I have a requirement that group of signals must be stable for at least Xns before the assertion of SignalQ. What would the property look like.
Can I use $stable or $change. But they require clock.

In reply to shals:

// I have a requirement that group of signals must be stable for at least Xns
// before the assertion of SignalQ. What would the property look like.
// Can I use $stable or $change. But they require clock.

You’ll need supporting logic to create a ghost signal for that group of signals.
For example, given the following requirement:
“a” stable for 2ns then @ (posedge clk) b |-> c;


    bit clk, a, b, c, va;  
    default clocking @(posedge clk); endclocking
    initial forever #10 clk=!clk; 
    
    always @(negedge clk)  begin // Supporting code for SVA 
        #8ns va<=a; 
    end 
  
    ap: assert property(@ (posedge clk) b && va==a |-> c);   
   

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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  1. VF Horizons:PAPER: SVA Alternative for Complex Assertions - SystemVerilog - Verification Academy
  2. http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf
  3. “Using SVA for scoreboarding and TB designs”
    http://systemverilog.us/papers/sva4scoreboarding.pdf
  4. “Assertions Instead of FSMs/logic for Scoreboarding and Verification”
    https://verificationacademy.com/verification-horizons/october-2013-volume-9-issue-3
  5. SVA in a UVM Class-based Environment
    https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment