How to write an asertion to check the clock frequency of clk_a & clk_b

SystemVerilog
,
1

i want to verify the frequency of clock a & clock b are same using an assertion.

what could be my reference clock.

i know how to check the frequency for a single clock by taking the time difference between posedge & negedge of clock.

how should be my approach, if i’m having 2 clocks.

Thanks in advance
Ravi

2

In reply to ravi shank:

Hello, this works on my side, any correction is more than welcome. This approach assumes clk has 50% of duty it will not work in case of different signal or duties (not really an hassle just need to change the negedge of clka or clkb with posedge).

Use local params to tune semiperiod of each clk.


`define mhz 1000
module twoclks_oneproperty;
  bit clka, clkb;
  
  // decide which clk runs faster
  localparam sta = 20;
  localparam stb = 20;
  
  // gen
  always #(sta*1ns) clka = ~clka;
  always #(stb*1ns) clkb = ~clkb;
  
  // support logic
  time starta, startb, endb, enda;
  bit compa, compb;
  bit fire;
 
  always @(posedge clka) begin
    starta = $time();
    @(negedge clka);
  	enda = $time();
    if(~compa) compa = 1;
  end

  always @(posedge clkb) begin
  	startb = $time();
    @(negedge clkb);
  	endb = $time();
    if(~compb) compb = 1;
  end
  
  // function to display time
  function void print_freq();
    $display("clka and clkb have different freq: clka_f: %f(MHZ), clkb_f: %f(MHZ)",((1.0)/(2*(enda - starta)))*`mhz,((1.0)/(2*(endb - startb)))*`mhz);
  endfunction
  
  assign fire = (compb & compa);
  
  property check_clks_have_equal_f();
    @(posedge fire)
    (((endb - startb) == (enda - starta)),$display("clka and clkb have same freq"));
  endproperty
  
  assert property(check_clks_have_equal_f) else print_freq();
    
  // controller
  initial begin
    #100;
    $finish();
  end
endmodule

In case of floating point frequencies (like 20.10 Mhz) then accuracy is needed (± yout_accepted_variation)