Hi,
I am verifying clock gate, which has clk_in, clk_en and clk_out.
How to write a logic which verifies : clock is not generated when input clock is present and clock is enabled.
Regards,
Srikanth.
Hi,
I am verifying clock gate, which has clk_in, clk_en and clk_out.
How to write a logic which verifies : clock is not generated when input clock is present and clock is enabled.
Regards,
Srikanth.
In reply to srikanth_manukonda:
I am verifying clock gate, which has clk_in, clk_en and clk_out.
How to write a logic which verifies : clock is not generated when input clock is present and clock is enabled.
How about assertions instead. Here I used a delayed version of the clk in the assertions to get away from glitches and use sampling regions that are stable. The clk_out is delayed from clk because of the gating.
import uvm_pkg::*; `include "uvm_macros.svh"
module m;
bit clk, clk_dly, enb, clk_enb, clk_out;
initial forever #10 clk=!clk;
ap_pos_enb1: assert property(@(posedge clk_dly) clk_enb |-> clk_out==1'b1 );
ap_neg_enb1: assert property(@(negedge clk_dly) clk_enb |-> clk_out==1'b0 );
ap_pos_enb0: assert property(@(posedge clk_dly) !clk_enb |-> clk_out==1'b0 );
ap_neg_enb0: assert property(@(negedge clk_dly) !clk_enb |-> clk_out==1'b0 );
always @(posedge clk) begin
if(enb) clk_enb <= 1'b1;
else clk_enb <=1'b0;
end
assign #1 clk_dly=clk;
assign clk_out = (clk_enb) ? clk : 1'b0;
initial begin
repeat(200) begin
@(posedge clk);
if (!randomize(enb) with
{ enb dist {1'b1:=1, 1'b0:=3};
}) `uvm_error("MYERR", "This is a randomize error")
end
$finish;
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
In reply to ben@SystemVerilog.us:
Ben,
I planning to implement this inside class. these assertions allowed inside classes.
thanks.
In reply to srikanth_manukonda:
In reply to ben@SystemVerilog.us:
I planning to implement this inside class. these assertions allowed inside classes.
Concurrent assertions are not allowed in classes. Why not using a SystemVerilog interface? That SystemVerilog interface need not be the DUT interface, it could be another interface that you define (e.g., a clock interface). I address this issue in several of my papers.
See my White paper: “Using SVA for scoreboarding and TB designs”
and a related issue at the Verification Academy the following paper
“Assertions Instead of FSMs/logic for Scoreboarding and Verification”
available in the verification-horizons October-2013-volume-9-issue-3
http://verificationacademy.com/verification-horizons/october-2013-volume-9-issue-3
and “SVA in a UVM Class-based Environment”
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
How do we verify clock gating using SVA with a formal checker tool?
Thanks,
Kanthi
In reply to kmeenal25:
See https://verificationacademy.com/courses/clock-domain-crossing-verification
In reply to dave_59:
You might also be referring to sequential equivalence techniques, which are used in such situations—see, for example, the DAC ’15 User Track best paper winner, by M V Achutha Kirankumar from Intel, RTL2RTL Formal Equivalence : Boosting the Design Confidence