How to use variable delay in SVA

SystemVerilog
, ,
1

Normally we use this method
$rose(a) |=> $stable(a)[*20];

But how to use this by using variable delay
int width = 20;
$rose(a) |=> $stable(a)[*(width)];

2

In reply to kolliparapavankumar:

https://verificationacademy.com/forums/systemverilog/assertion-variable-declaration-sva-0