How to use Parameterized Classes?

SystemVerilog
1

Hello SV User group,
I wanted to ask a question about how to properly design and instantiate a Parameterized System Verilog Class. I would like to put my class definitions in a package and then uses that package in my program code to instantiate parameterised Class objects.

For example:


package my_Package;

 typedef bit[31:0] MyData_type;
 typedef int Another_type;

 class my_class #(parameter type T=MyData_type);

   T r1;
   T r2;

   .. define all Class functions etc

 endclass

endpackage

module my_modulue;

import my_package::*;

program my_program;
   
   my_class #(MyData_type) obj1;
   my_class #(Another_type) obj2;


   initial begin
      obj1 = new ( ...);
      obj2 = new ( ...);

   end

endprogram

endmodule

What is the preferred way to do this sort of thing and will it work in all Simulators ?

Thanks for your help,
Dr Barry H