How to use numbered identifiers in a loop

SystemVerilog
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1

Let’s say I want to connect a bus, similar to the below, where the name of the wire includes numbering:

wire bus[500:0];
assign bus[0] = my_wire_0;
assign bus[1] = my_wire_1;
…
assign bus[500]= my_wire_500;

Is there a way to do this in a loop (generate or otherwise)? Especially interesting if the width is a parameter and not a constant.
My attempts have failed as:

  1. I couldn’t modify the wire name identifier at the correct part of the process
  2. I tried using concatenation using macros (``), but macro elaboration is done before the loop unrolling and thus fails.
2

In reply to vlsiraptor:

I don’t believe you can do this directly in Verilog/SV (Unless Dave decides to surprise me and teach me one more today :-)). However, a simple pre-processor can do this:

module m();
  wire bus[500:0];

  //@ for my $i (0..500) {
  assign bus[$i] = my_wire_$i;
  //@ }
endmodule : m

Then use the vpp.pl from: http://www.beyond-circuits.com/wordpress/vpp-pl-man-page/

I used it like:


perl vpp.pl inp_with_meta.v -perl

Sample output (Of-course not showing 501 lines :-) )


module m();

  wire bus[500:0];

  assign bus[0] = my_wire_0;
  assign bus[1] = my_wire_1;
  assign bus[2] = my_wire_2;
  assign bus[3] = my_wire_3;
  assign bus[4] = my_wire_4;
  assign bus[5] = my_wire_5;

HTH
Srini
www.verifworks.com