How to use enum data type in constraints?

SystemVerilog
1

Hi.

I’m trying to understand constraints with enum type as the below,

Picture
reference mentor

But I don’t undersatnd why I got the error message, how to use enum data type into constraint?

cmd = POWER_ON;
|
xmvlog: *E,EXPSMC (testbench.sv,31|9): expecting a semicolon (‘;’) [SystemVerilog constraint block item].
}




typedef struct {
rand bit OFF;
rand bit START;
rand bit ANY;
  
}cmd_state_s;

typedef enum {
  POWER_ON,
  POWER_OFF,
  SW_GLOBAL_RST,
  GPIO_GLOBAL_RESET
} prj_cmd_e;

class A;
 rand cmd_state_s state;
 rand prj_cmd_e cmd;
  
 rand bit [7:0] pattern;
 rand bit mode;
  
 constraint off_c{
   if(state.OFF)
     cmd = POWER_ON;
  }
endclass


module test();
initial begin
  for (int i =0; i< 10; i++) begin
  A a =new();
  a.randomize();

    $display("cmd: %h", a.cmd);
  end
  
end
endmodule
2

In reply to UVM_LOVE:

You get an error because your code is wrong. In a constraint, ‘==’ is the equality operator, not ‘=’.


class A;
 rand cmd_state_s state;
 rand prj_cmd_e cmd;
 
 rand bit [7:0] pattern;
 rand bit mode;
 
 constraint off_c{
   if(state.OFF)
     cmd == POWER_ON;
  }
endclass