Hi All,
$rose(b) |-> a[*3];
Whenever the b goes 0 to 1. The next 3 continues clock cycles a should be true.
$rose(b) |-> a[*value];
If i am give value instead of 3.
i am getting error like "Illegal operand for constant expression".
Because my case 3 is not fixed.It's changing at any time.
So any idea to how to check this scenario.
SOLUTION: Reference ii (at end of this paper) provides a solution for handling dynamic delays an repeats using tasks. However, in the Forums: SystemVerilog | Verification Academy forum, a user brought up a very interesting alternative that uses a package; it is presented here. The concept is very simple, the repeat or delay sequence is saved in a package with two defined sequence declarations that include arguments. http://SystemVerilog.us/vf/sva_delay_repeat_pkg.sv