How to use assign inside $test$plusargs in systemverilog?

In my code, I want to do some connections using assign statement for all my tests except one test for which I added a runtime argument “HB_CONN_DISABLE” in my testlist. When I code as follows,I get the below error

if (!$test$plusargs(“HB_CONN_DISABLE”))
begin
assign iol.hb_valid_in = dp_if_tx_inject.hb_bar_val_in;
assign iol.hb_in = dp_if_tx_inject.heartbeat_in;
end

Error-[V2KGEUV] Unknown or bad value for genvar
-I-:/nfs/hd/disks/mgr_0240/…soc_post.sv, 543
Instance/Generate block name: iolc_tb
-I-: Elaboration time unknown or bad value encountered for generate if-statement
-I-: condition expression.
-I-: Please make sure it is elaboration time constant.

I also tried something like below, but in this case it doesn’t recognize hb_bar_param in this line if(hb_bar_param==0) may be because by that time the parameter doesn’t get the value

initial begin
if ($test$plusargs(“HB_BAR_TI_CONN_DISABLE”))
begin
parameter hb_bar_param=1;
end
else
begin
parameter hb_bar_param=0;
end
end

if(hb_bar_param==0)
begin
assign statements…
end

I also tried using assign with ternary operator like the following

assign iol.hb_valid_in = ($test$plusargs(“…somthing…”)) ? (… some value …) : (… some other value …);

but in that case I will still end up assigning something if the testplus args is false, but for me the requirement is that I dont want to assign at all if the testplus args is there, please help me with this problem

In reply to GC:
You could do

assign iol.hb_valid_in = $test$plusargs("...somthing..") ? 'z : (...some_value...);

In reply to dave_59:

I tried using “z” since its a wire but in that case i see it stays z, the value to this wire “hb_valid_in” is being provided from the sequence in this particular testcase and I don’t want it to be overriden by this assign. In this case its not taking the value from sequence but it stays z but if I don’t do assign at all for this particular case, it works so I was looking for a way to not do these assigns for a particular test, not sure if this is doable.

In reply to GC:

Now you’re adding additional information that wasn’t in the original question. Can you create a mock-up self-contained example of all that is involved with driving this signals. Driving a wire with 'z should be the same as not driving it at all.

Sorry I think I missed that, actually if I take example of just this one signal “iol.hb_valid_in”, in one of my tests I want to drive it through one of the saola functions which are inbuilt for me which do backdoor write on this signal in my sequence but these assign statements if they are exercised, then they override the value that I want to drive through my sequence for this particular test. Basically what I observed is that the value driven from saola function in my sequence can still be seen on this wire but is not propagated to other net it is connected to further in the rtl and if I comment out these assign statements, the value is propagated so I wanted to selectively use assign statements for this test .

If I make it z using assign, I am unable to drive using the sequence and it stays z.