How to test your assertions

I am working on Protocol checker VC. For this I have written some assertions. Now I have to “test this assertions”. Does it mean I have to write test cases to verify my assertions? Please brief me as I am not getting the exact meaning of testing the assertions.

In reply to aditya raja:

It would be good if you have the flexibility to easily write/modify tests to hit these assertions and confirm they are indeed working as intended.

Another idea is to reverse/negate the assertion, and that should cause all good tests to fail with the assertion.

In reply to aditya raja:
Aside from having code reviews, I quickly test the assertions in a module using constrained-random tests. I use the following template as a model where I put my assertions and tune the constraints. This template is saved using https://www.phraseexpress.com/ Text Expander and Autotext Software (free for single-use, really a very useful software):


import uvm_pkg::*; `include "uvm_macros.svh" 
module top; 
	bit clk, a, din;  
	default clocking @(posedge clk); endclocking
	initial forever #10 clk=!clk;   
// assertions go here <<<<<<<<<<<<<<

 initial begin 
     repeat(200) begin 
       @(posedge clk);   
       if (!randomize(a, din)  with 
           { a dist {1'b1:=1, 1'b0:=3};
             din dist {1'b1:=1, 1'b0:=2};

           }) `uvm_error("MYERR", "This is a randomize error")
       end 
       $finish; 
    end 
endmodule   

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr


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Thank you so much.