Hi folks,
I am trying to understand how SV Macro get processed. Here are the two questions:
1. Why undef cannot be there?
2. Interestingly different simulators output differently on stringify macro. Any comments?
`define SN _ma
`define NAME_S(A) tom``A
`define NAME `NAME_S(`SN)
`define STRF(PATH) `"PATH`"
//why cannot undef here, I assume that `SN already expand for Macro NAME definition
//`undef SN
module tb;
string tom_ma = "tom_ma";
initial $display("%s", `NAME);
initial begin
//why verdi expand to "tom_ma", VCS print out `NAME_S(_ma) different from other simulators??
$display("%s", `STRF(`NAME_S(`SN)));
//expand as expect
$display("%s", `STRF(`SN));
end
endmodulehttps://www.edaplayground.com/x/PDr3
