How to start verification in big projects

SystemVerilog
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  1. What are the steps that need to take care of design verification from scratch(own code)??
  2. What are the steps need to care for design verification using VIP from scratch??
    Please give clarity to the above queries.
2

In reply to Subbi Reddy:

  1. What are the steps that need to take care of design verification from scratch(own code)??
  1. What are the steps need to care for design verification using VIP from scratch??
    Please give clarity to the above queries.

Great question! So what do we know?

    1. You have a new set of requirements for a design
    1. The design incorporates some IPs

Verification starts from the onset of a project. What is being verified is that the design requirements are met through all aspects or phases of the design, including its implementation and system integration. So what does that mean? That’s quite a big bite of information to chew.
In 2000, Synopsys and Mentor Graphics Released Open Measure of Reuse Excellence “OpenMORE" Reference Program for Evaluating IP Design Reuse and Verification.

What is interesting about OpenMore is that is a a spreadsheet that addresses the many aspects of a design, from conception thru verification, deliverable, and soft Macro, and thus provides items to consider in the process.
In 2001 I wrote a book “Component Design by Example: … a Step-by-Step Process Using VHDL with UART as Vehicle” Amazon.com systemverilog.us/cmpts_free.pdf that uses a UART as a vehicle It demonstrates through models the design process, including the definition of the requirements, the architectural plans, verification plans. The value of this book is not in the actual chip model, but the process, and you may benefit by scanning through its contents. I filled the OpenMore spreadsheet as a demo (http://systemverilog.us/vf/cmpts.zip

A very important tool in verification is the use of SystemVerilog Assertions (SVA) (https://rb.gy/upqrnl ). With my extensive experience, discussions, and published papers, I definitely encourage the use of SVA during the design process, and that is also used in verification. I see two aspects in the use of SVA. The first aspect address the requirements and assumptions where the subpartitions and chips are viewed as black boxes and thus must meet the requirements and assumptions imposed on those boxes. In that case, SVA is written in interfaces. The second aspect of SVA addresses the actual design requirements and assumptions imposed by the designer; it reflects his/r understanding of what needs to be done. The use of the SystemVerilog checker bound to the design unit is a good approach to write SVA. SVA expresses the properties in a very concise manner, but if you want to better understand a possible underlying implementation, read my paper “Understanding the SVA Engine”, https://verificationacademy.com/verification-horizons/july-2020-volume-16-issue-2

Companies that design very complex chips, such as CPUs or custom large designs, use formal verification that makes use of SVA code. I like the book “Formal Verification: An Essential Toolkit for Modern VLSI Design 1st Edition, Kindle Edition”, by Erik Seligman https://rb.gy/bmgt3k You definitely need to consider formal verification.
Other tools to consider is emulation, as this is better adaptable for considering how the design integrates well with software.
For simulation, UVM is widely adopted and should be considered to generate constrained-random tests and to assess coverage. Many EDA companies provide tools for the automation process in verification. You need to do your own research on this topic, by you already know who the EDA vendors are, and they will be thrilled to educate you.
Another aspect to consider is to hire consultants in this field. In the writing of my books I called on Srinivasan Venkataramanan for support and co-authorship because he has experienced in his career as a designer, application engineer, teacher, and entrepreneur of his own consulting and teaching company. Srini Home - My cvcblr is very knowledgeable in this whole design and verification field. Anyway, hiring consultants can provide good insights. When I remodeled my house, I hired consultants and a decorator to maximize my returns and enjoyment in the use of the house.

I welcome comments about this topic.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  2. Free books: Component Design by Example https://rb.gy/9tcbhl
    Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
  3. Papers: