How to set a flag for one clock cycle on request

SystemVerilog
1

Hi,

I am looking for some suggestions/minor adjustments to my code.
I want to set a flag for one clk cycle whenever the request is asserted(0->1). if the req is high for n number of continuous cloks then just set the flag only for the first clk cycle.
Thanks in advance.


forever @(posedge m_vif.uclk iff m_vif.Req == 1) begin
  flag = 1;
  @(posedge m_vif.uclk);  //after one cycle clear the flag
  flag = 0;
  @(posedge m_vif.uclk iff m_vif.Req == 0); //wait till posedgeclk and req is 0
  // or
  // wait(m_vif.Req == 0);
end

// problem with my code is 
// 1st clk Req = 1
// 2nd clk Req = 0
// 3rd clk Req = 1
// in this case the last event @(posedge m_vif.uclk iff m_vif.Req == 0); will evaluate to false and my loop would be waiting for Req == 0.
// one solution i could think here is removing posedge clk like --> wait(m_vif.Req == 0); 
// so that it completes loops and goto start of forever loop for next clock
// Question:
//    is there a better solution! if i want to synchronize the logic with clk like above in code. if so,  how do i do ?
2

In reply to NaveenReddy:

Hi,

If I understand your problem well what you need to do is:

forever begin
   @(posedge m_vif.Req);
   flag = 1;
   @(posedge m_vif.uclk);
   flag = 0;
end
3

In reply to NaveenReddy:

I would do just

delay the request by one clock then (request) xor (delayed request)

4

In reply to PedroCavalcante:

if the request is high for multiple clock cycle then you will always be asserting the flag every other posedge of the clock which is not correct.

The required output is flag should be asserted high once and ony for one clock cycle when the request is asserted.

Also, though i could achieve the solution by looking at the signals like below i want something to get the signals in sync with clock.


forever begin
   @(posedge m_vif.Req);
   flag = 1;
   @(posedge m_vif.uclk);
   flag = 0;
   wait(m_vif.Req == 0);
end
5

In reply to NaveenReddy:
You should be using non-blocking assignments.

forever @(posedge m_vif.uclk iff m_vif.Req == 1) begin
  flag <= 1;
  //after one cycle clear the flag
  flag <= @(posedge m_vif.uclk) 0;
  @(posedge m_vif.uclk iff m_vif.Req == 0); //wait till posedgeclk and req is 0 
end