How to set a per bit baud rate?

SystemVerilog
1

hi
I am currently working in a UART design.assume the baud rate =9600, and i am using 1 start bit,8 data bit,1 parity bit and 1 stop bit. So i am used total of 11 bit, so 9600/11=873.727273 per bit duration.So how to set the delay of 873.727273 per bit.

using the timescale

Thanks in advance

2

In reply to Rajaraman R:

What are you trying to calculate? Baud rate means ‘bits per second’. The number of start/data/parity/stop bits has no effect on baud rate. For 9600 baud, you want to tx/rx 9600 bits per second.

3

In reply to cgales:

Thanks for replay

Overall baud rate is a 9600. But i want a single bit duration. Because of the UART reciever only recieve a mid of the time period.

4

In reply to Rajaraman R:

If you have 9600 b/s, then single bit duration would be 1/9600.
Eleven bits duration would be 11/9600.

5

In reply to Rajaraman R:

What will your system clock be running at? From the system clock you can determine how many cycles you will need wait before sampling.

If the UART is running at 9600 Baud, then each bit is changing at 1/9600(seconds) which is 104167ns. So every 104167ns is when the bit changes.