How to return variable in function

SystemVerilog
,
1

I want to assign the function return value to the module variable ‘data’.
but the ‘data’ variable is showing 1 as output instead of the function return value.
did I make mistake to return value?
how can I achieve ‘data’ as a function return value?


module task_function_session_ex_5;
  
  //bit [1:0]address;
  byte _byte[4];
  bit [31:0]data;
  parameter int MSB=100,LSB=0;
  
  initial
    begin
     
      foreach(_byte[i])
        _byte[i]=$urandom_range(MSB,LSB);
        
      data=byte_to_word(_byte,data);
      $display("data=%p",data);     
    end
function byte_to_word(//input bit [1:0]add,
                      input byte _byte[4],
                      output bit [31:0]wdata
                     );
  bit [31:0]temp;
 
      foreach(_byte[j])
        temp[8*j+:8]=_byte[j];
  $display("temp=%b",temp);
  //assign wdata=temp;    
  return temp;
endfunction: byte_to_word
endmodule
2

In reply to jishan_bukhari:

In the future, please use code tags to make your question more readable. I have added them for you.

Your function declaration has no return type. Per the LRM, it should be:

function < return_type > < function_name >(< arguments >);

Since you have no return type specified, it defaults to a single bit, hence the ‘1’ being returned.

3

In reply to cgales:

thank you so much sir for your guidance.i will keep in my mind what u have suggested.