How to resolve the warning "The expression "xaction_1.example_struct.trans" is a member of a packed structure and cannot be used in a solve-before constraint."

SystemVerilog
, , ,
1 
typedef struct packed {
  logic [5:0] ctr;
  logic [2:0] source;
  logic [5:0] addr;
} pkt_a;


typedef struct packed {
  pkt_a LOC_ID;
  pkt_a PARENT_ID;
  pkt_a TRANS_ID;
} t_struct;

class xaction;
  rand t_struct example_struct;
endclass

class xaction_types;
  rand xaction xaction_1;

  constraint t_struct_c {
    solve xaction_1.example_struct.TRANS_ID before xaction_1.example_struct.LOC_ID
  }
endclass
2

In reply to RUDD_V:

It would help to explain what you are trying to achieve with the solve-before construct. The solve-before construct can only modify the distribution of results based on the biases of other constraints. You have no other constraints.

Also, local is a reserved keyword and cannot be used for a field name.