Hi,
I’d like to replace one module in my design with another module defined and instantiated in my testbench (and keeping the same instance name). I’d like to use SV bind for that, as show in this example:
— design —
module block_0 ();
block_0 i_block_0 ();
— testbench —
module block_0 ();
bind dut block_0 i_block_0();
I don’t know if it is possible to do that without resorting to `ifdefs.
Thank you !
In reply to agiulietti:
The
bind construct inserts instances into your design. It cannot be used to replace them.
The easiest alternative would be to modify the compilation file path to point to the actual module you want compiled in. You can set up links or environment variables to help there.
Another option is get your two module versions compiled into two different libraries and have the search path specify which library to pick it up from, or use Verilog config block the specify explicitly which library to use. The use of libraries involves some tool specific details. You’ll need to look up that information in your tool’s documentation.
In reply to agiulietti:
Binding a module to another design is like poking or projecting an instantiation of that module into the unmodified target file. It is not “replacing” some designs. This paper is good one to grasp about bind.
In reply to sharvil111:
Thanks a lot sharvil111 and Dave for the answers. I will have to modify the compilation settings then.
Just to clarify the context in which I’d like to replace modules in the DUT. When designing sensors the input to your DUT is not an actual port, but some kind of energy (eg. light, noise, vibration) that is converted into quantities within the DUT. Normally when simulating your system you need a model (probably written in Verilog-AMS) which performs this conversion from some kind of input (eg. input file).
When designing a SV testbench you want to take advantage of SV constructs to model your conversion instead of relying on the legacy model that is instantiated within the DUT, but still keeping the option to choose between them (legacy and SV).
In reply to sharvil111:
The link seems to be no more active, can you share the paper Title? I will try to find it somewhere else.
-Saurabh
In reply to saurabh.sa27:
I somehow forgot the content of that link. Here is a link to Cummings paper for SVA which describes bind nicely. This paper also describes bind from a testbench perspective.