How to randomize delay and assign it to clock

SystemVerilog
, , ,
1

Hi,

I want to randomize delay between (0, 1.28)ns and apply it to clock, any idea how can I do that?

I tried $urandom_range, but it returns only integer value, how can I return values between (0, 1.28)ns?

Thanks!

2

In reply to rushabhmangukiya27:

$urandom_range(128)/100ns
3 
shortreal rand_val;
  rand_val = $urandom_range(128)/100ns;
  `uvm_info("DELTA", $sformatf("Randomized delta: %f", rand_val), UVM_NONE)
  #rand_val itf.clk_itf[CLK_UNSHAPED].clk =~ itf.clk_itf[CLK_UNSHAPED].clk;

Can I do something like this? if yes then I’m getting following error:
Following verilog source has syntax error :
136: token is ‘=’
rand_val = $urandom_range(128)/100ns;

Thanks!

4

In reply to rushabhmangukiya27:

You are not showing enough code. What kind of procedural block is this statement located in?

This works for me

module top;
  initial begin
    real rand_val;
    rand_val = $urandom_range(128)/100ns;
    `uvm_info("DELTA", $sformatf("Randomized delta: %f", rand_val), UVM_NONE)
  end
endmodule

and outputs

UVM_INFO testbench.sv(7) @ 0: reporter [DELTA] Randomized delta: 0.380000
5

Thanks, its working now.