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  • How to randomize delay and assign it to clock

How to randomize delay and assign it to clock

SystemVerilog 6448
#constraint ... 82 #0 delays 3 #systemverilog #clock ... 2
rushabhmangukiya27
rushabhmangukiya27
Forum Access
6 posts
August 10, 2022 at 8:57 am

Hi,

I want to randomize delay between (0, 1.28)ns and apply it to clock, any idea how can I do that?

I tried $urandom_range, but it returns only integer value, how can I return values between (0, 1.28)ns?

Thanks!

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Solution

Solution

dave_59
dave_59
Forum Moderator
10890 posts
August 10, 2022 at 9:18 am

In reply to rushabhmangukiya27:

$urandom_range(128)/100ns

— Dave Rich, Verification Architect, Siemens EDA

rushabhmangukiya27
rushabhmangukiya27
Forum Access
6 posts
August 10, 2022 at 9:40 am 

shortreal rand_val;
  rand_val = $urandom_range(128)/100ns;
  `uvm_info("DELTA", $sformatf("Randomized delta: %f", rand_val), UVM_NONE)
  #rand_val itf.clk_itf[CLK_UNSHAPED].clk =~ itf.clk_itf[CLK_UNSHAPED].clk;

Can I do something like this? if yes then I'm getting following error:
Following verilog source has syntax error :
136: token is '='
rand_val = $urandom_range(128)/100ns;

Thanks!

dave_59
dave_59
Forum Moderator
10890 posts
August 10, 2022 at 10:05 am

In reply to rushabhmangukiya27:

You are not showing enough code. What kind of procedural block is this statement located in?

This works for me

module top;
  initial begin
    real rand_val;
    rand_val = $urandom_range(128)/100ns;
    `uvm_info("DELTA", $sformatf("Randomized delta: %f", rand_val), UVM_NONE)
  end
endmodule

and outputs
UVM_INFO testbench.sv(7) @ 0: reporter [DELTA] Randomized delta: 0.380000

— Dave Rich, Verification Architect, Siemens EDA

rushabhmangukiya27
rushabhmangukiya27
Forum Access
6 posts
August 10, 2022 at 12:50 pm

Thanks, its working now.

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