How to pass multi-bit variable in a SVA property's arguments?

SystemVerilog
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1

For single bit case - a property and its usage would be like the one below:


      logic Req_IP,Ack_IP;
                    
      property SAMPLE_1(Req, Ack);
        $rose(Req)|-> $rose(Ack)
      endproperty

      SINGLE_BIT: assert property(SAMPLE_1(Req_IP, Ack_IP));

I am trying to achieve for multi-bit. Something like the one below…


logic [31:0] sData_IP, Ref_Value_IP;
logic Req_IP;

property SAMPLE_2(Req, /*How to mention width ?*/sData, /*How to mention width ?*/ Ref_Value);
  $rose(Req)|=> (sData == Ref_Value)
endproperty

MULTI_BIT : assert property(SAMPLE_2(Req_IP,sData_IP, Ref_Value_IP));
2

In reply to rshrig:

For sequences, properties, and checkers, there is no need to specify an argument’s type. Arguments are just symbolic references similar to the way macro arguments work.

If you want to specify a particular argument type, you can do so the same as you would in a function or task.

property SAMPLE_2(Req, logic [31:0] sData, Ref_Value);

This is all explained in the LRM section 16.8 Declaring Sequences.

3

In reply to dave_59:

I have a query. Suppose I want to pass the width of the signal via the property’s formal argument as below, Is it legal?

property SAMPLE (WIDTH);
@(clk) signal to check == data[WIDTH-1:0]
endproperty

4

In reply to atanu.biswas:

As long as the actual argument is legal for what gets substituted for WIDTH. (e.g. a literal constant or parameter).

5

In reply to dave_59:

Thank you so much Dave.