How to pass the make file parameter value to abc_tb (top file)!

SystemVerilog
1

Hi All,

I need to pass the one parameter value to the top file (abc_tb), and depending on the parameter value i need to connect 2 different signals as mentioned below

abc_tb;
  
  import uvm_pkg::*;
  ...
  ...
  ..
  import x_pkg::*;

  integer TA;

  initial begin
   if(!$value$plusargs("INTG=%d", TA))
      $display("NO values got");
   else 
      $display("got value TA= %d", TA);
  end

  assign x_w[1] = (TA > 23) ? a_if:b_if;
  ....
  ...

 endmodule

and passing TA value from makefile as below
MAKEFILE ::

clean:
      abc
  prepare :
     abc
  compile :
    vlog -64 \
    -sv \
    +INTG=25 \
     ..
     ..
opt :
  abc
 
sim:
  vsim -64 \
  ..
  +INTG=25 \
  ..
 
all : optize sim

**But i am not getting the TA value ?
**

2

In reply to RavindraShiradone:

This should have worked. Use
make -n sim to see the exact command line being used, or look at the transcript.

3

In reply to dave_59:

No,its not working ! Still abc_tb is not getting the TA value !

when i used “make -n sim”, below result came :
vlog -64
-sv
+INTG=25
…
…
vopt -64 abc_tb -o optimized
+acc
+INTG=25
…
…
vsim -64
-i “+UVM_TESTNAME=xyz” “+UVM_VERBOSITY=UVM_LOW”
“+SV_SEED=0”
+INTG=25
…
…

4

In reply to RavindraShiradone:

I suggest making a simple example with just the initial block you have shown.

module top;
   int TA;
initial begin
   if(!$value$plusargs("INTG=%d", TA))
      $display("NO values got");
   else 
      $display("got value TA= %d", TA);
  end
endmodule

Then try executing your simulation commands manually. Then with a simple make file. I think it would be much easier for you to find some local help than trying to debug this via a forum. And the Mentor sponsored forum is not for tool specific help.

5

In reply to dave_59:

Thank you dave_59, Its working.