How to Pass Constructed String Name Inside a Generate Statement?

SystemVerilog
,
1

Hello !

Is there a way I can pass constructed string name inside a generate block ?

  1. Below is a working example, where I am trying to bind a module which has an interface to be passed to respective testbench path.
  2. Also use a macro wrapper to configure it.
  3. Shown couple of methods to do the process:
    a. Method 2: Is straightforward way with hard coded string name and works fine.
    b. Method 1: In this method I am trying to create a generate statement to configure it. But I am un-successful to get it going.

Would like to know, if there is a cleaner way to pass constructed string inside the generate statement ? Using some string construction method ? or there is not other way at all ? Please let me know.


`ifdef HOW_MUCH 
    parameter HOW_MUCH = (`HOW_MUCH==2)?2 : 1;
`else 
    parameter HOW_MUCH = 2;
`endif


`define probe_bind(HIERNAME, WRAPNAME, INTF, INTFNAME, INTFHIER)\
    bind ``HIERNAME`` probe_wrapper #(.intf_name(`"INTFNAME`"), .intf_hier(`"INTFHIER`")) probe_wrapper_``WRAPNAME`` (.prb_intf(``INTF``));
`define STRINGIT(s) `"s`"

interface probe_intf();
  logic clk;
endinterface: probe_intf 

module probe_wrapper #(
  parameter string                    intf_name  = "probe_vif",
  parameter string                    intf_hier = "hierarchy")
 (probe_intf                          prb_intf);

  initial begin
    $display("probe_wrapper: intf_name: %0s For Hierarchy: %0s\n", intf_name, intf_hier);
  end
endmodule: probe_wrapper 

module tb_top;
 probe_intf prb_intf[HOW_MUCH]();

 // Method : 1
 genvar num;
 for (num=0; num<`HOW_MUCH; num++) begin 
   `probe_bind(tb_top, $sformatf("wrap_%0d", num), prb_intf[num], $sformatf("probe_vif_num%0d",num), *);
 end 

 // Method : 2 
/*`ifdef HOW_MUCH 
 if (`HOW_MUCH >= 1) begin
  `probe_bind(tb_top, wrap_0, prb_intf[0], probe_vif_num0, *)
 if (`HOW_MUCH >= 2) begin
  `probe_bind(tb_top, wrap_1, prb_intf[1], probe_vif_num1, *)
 end
 end
`endif*/

endmodule: tb_top
2

In reply to desperadorocks:

You need to remember that macros get expanded into text before any SystemVerilog code gets parsed. But your bigger problem is you can’t use dynamic strings to build identifier names.

Its not clear why you need to use
bind from your example; you can just use the generate-for loop to instantiate probe_wrapper directly. In your actual case, you might have to create a module that takes the array of interfaces as a port, and bind that to where you needed it, and inside that module, put the generate loop.