How to overwrite assertions of a class that is instantiated in other class

SystemVerilog
1 

class first;
rand bit [3:0] a;

constraint a_ { a inside [3:5] ;}

endclass

class second;
first f;
function new();
f=new();
endfunction

endclass

could you please help in understanding how to overwrite the first class constraints in second class.

2

In reply to srbeeram:

It would help if you would explain by showing us code where you expect to call randomize() from.

3

In reply to dave_59:
Hi Dev please find the following code


class first;
rand bit [3:0] a;
 
constraint a_ { a inside [3:5] ;}
 
endclass
 
class second;
first f;
function new();
f=new();

endfunction

function body()
f.randomize();
endfunction
 
endclass
4

In reply to srbeeram:
That is still not enough code to show how randomize() gets called, and at what point relative to randomize() do you know when you want to override the constraint.

class first;
  rand bit [3:0] a;
  constraint a_ { a inside [3:5] ;}
endclass
class first_override extends first; 
  constraint a_ { a inside [7:9]] ;}
endclass
class second;
  first f;
  function new();
    f=first_override::new();
  endfunction
  function body()
    f.randomize();
  endfunction
endclass