Hello,
I have a VHDL entity with many generics including ‘std_logic’, ‘boolean’, and ‘natural’ types. I’m having trouble overriding parameters due to type mismatches, verror:
(vsim-3351) Invalid value for generic. Not using this value.
When I pass values where I instantiate the VHDL entity in my SV module, for example:
#(.MY_STD_LOGIC_GENERIC( 3’d2 ))
it works fine, but when I override the generic on the vopt command line (using the “-G” option) like:
-G MY_STD_LOGIC_GENERIC=2
then I get the previously-mentioned error.
I couldn’t find where the Questa 10.2c User Manual describes how to format the command line for the different data types. Any ideas how I can override values on the command line?
Thanks!
Victor
Note that neither “3’d2” nor “2” are actually valid values for a STD_LOGIC data type.
In your SV parameter(generic) over ride, the 3’d2 is getting trimmed and just the LSB is getting passed.
For your command line over ride, it does not do this sort of trimming or any type conversion, the value passed must be a legal value for the generic type being used.
I would expect something like
-GMY_STD_LOGIC_GENERIC=1
to work.
If you are still having trouble, I would recommend contacting your local Mentor Support representative they will be able to help you more with specific tool usage issues.
In reply to alexgran:
Alex, thank you for your prompt response!
Why do you say that the value of “2” is not valid?
From the Questa User Manual:
Passing parameter values from Verilog or SystemVerilog to a VHDL generic of type std_logic is slightly different than other VHDL types. Note that std_logic is defined as a 9-state enumerated type... To be able to correctly set the VHDL generic to any of the nine states, you must set the value in the Verilog instance to the element (positional) value in the std_logic enum that corresponds to the std_logic value (that is, the position not the value itself). For example, to set the generic to a ‘U’, use 1’b0, to set it to an ‘X’, use 1’b1, to set it to ‘0’, use 2’b10. Note that this only applies to std_logic types -- for std_logic_vector you can simply pass the value as you would normally expect.
[br]I can show that this is true when I pass a value at instantiation, for example:
#(.MY_STD_LOGIC_GENERIC( 3’d6 )) will equal ‘L’
it just doesn’t seem that vopt interprets the number (positional value) from the command line correctly.
I have experimented and found that I can override MY_STD_LOGIC_GENERIC with any value (eg: ‘0’, ‘1’, ‘W’, ‘X’) from the command line just by saying, for example,
-G MY_STD_LOGIC_GENERIC=W
and that I can override a std_logic_vector as such: (note the reuquired double-quotes!)
-G MY_STD_LOGIC_VECTOR_GENERIC=“24’hdefa17”
but what about other types?
[br]As I mentioned, my entity also has boolean generics and I read on another forum that boolean was like the std_logic type in that it is an enum and you simply refer to the positional value - can anyone confirm this? My experiments with setting the boolean generics have all failed.
Thanks!
In reply to v2skully:
I found how to override the boolean type from the command line.
For the edification of everyone else, this works:
-G MY_BOOLEAN_GENERIC=TRUE
It doesn’t matter if the value is upper- or lower-case.
[br]PS: I know I tried that - idk why it didn’t work before but it’s working now…
I can’t get the override to take the value.
This is my command;
vsim -i -sv_seed random “+UVM_TESTNAME=subenv_addr_walk_test” -permit_unmatched_virtual_intf “+notimingchecks” -suppress 8887 -solvefaildebug -solvefailtestcase -mvchome /rfs/apps/eda/mentor/questa_vip/10.6b -L pf_lib -t 1ps -uvmcontrol=all -msgmode both -classdebug -assertdebug “+uvm_set_config_int=*,enable_transaction_viewing,1” -do " set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; radix hex showbase; do breakpoints.do; " optimized_debug_top_tb -GG_INIT_INTRO_ENABLE=FALSE
I found the generic in question during a simulation and copied/pasted the name into the command. I’ve tried quotes around FALSE and no quotes. When I run the above command and check the generic value after the breakpoint, it’s still set to the default TRUE
The RTL has this line when instantiating the component.
GENERIC MAP(
G_INIT_INTRO_ENABLE => TRUE,
The entity of this component has default true also
GENERIC(
G_INIT_INTRO_ENABLE : boolean := TRUE;
I think the above and my command fall into the what the Reference Manual says I can do. Could optimization be playing part in my generic not getting overridden?
From the reference manual:
-G= …
(optional) Same as -g (see above) except that it will also override generics/parameters that
received explicit values in generic maps, instantiations, or from defparams.
This argument is the only way for you to alter the generic/parameter, such as its length,
(other than its value) after the design has been loaded.
— Name of a generic/parameter, exactly as it appears in the VHDL source (case is
ignored) or Verilog source. Name may be prefixed with a relative or absolute hierarchical
path to select generics in an instance-specific manner. For example, specifying -G/top/u1/
tpd=20ns on the command line would affect only the tpd generic on the /top/u1 instance,
assigning it a value of 20ns. Specifying -Gu1/tpd=20ns affects the tpd generic on all
instances named u1. Specifying -Gtpd=20ns affects all generics named tpd.
— Specifies an appropriate value for the declared data type of a VHDL generic or
any legal value for a Verilog parameter. Make sure the value you specify for a VHDL
generic is appropriate for VHDL declared data types. Integers are treated as signed values.
For example, -Gp=-10 overwrites the parameter p with the signed value of -10.