This is one of largest remaining holes in the SystemVerilog LRM—covergroups are not extensible.
For this particular covergroup functionality, it’s possible to put the bin values in an array before constructing the class, and setup the array to the values you want.
bit [7:0] a_binset[];
bit [2:0] b_binset[];
class abc;
bit [7:0] a;
bit [2:0] b;
covergroup cg ;
a_cp: coverpoint a {
bins abins[] = a_binset; }
b_cp: coverpoint b {
bins bbins[] = b_binset; }
endgroup
function new();
cg = new();
endfunction
endclass
module tb;
abc abc_h;
initial begin
a_binset = {250,255};
b_binset = new[8];
foreach(b_binset[ii]) b_binset[ii] = ii;
abc_h = new;
repeat(5) begin
abc_h.a = $urandom;
abc_h.b = $urandom;
abc_h.cg.sample();
end
end
endmodule
If you cannot figure out a way of working with a single covergroup, then you need to construct two covergroups and set the weight of the coverpoint you want to override to 0. You also need make sure both covergroups get sampled.
If I confirm, do you want to override cover group of child class over parent, correct?
If yes,then can you modify your code little bit as mentioned below and run again. It works.
class abc;
bit [7:0] a;
bit [2:0] b;
covergroup cg ;
a_cp: coverpoint a;
b_cp: coverpoint b;
endgroup
endclass
class xyz extends abc;
covergroup cg ;
a_cp: coverpoint a {
bins a_1 = {255};
bins a_2 = {250};
}
endgroup
function new();
cg = new();
endfunction
endclass
module tb;
xyz xyz1 = new();
initial begin
repeat(5) begin
xyz1.a = $urandom;
xyz1.b = $urandom;
xyz1.cg.sample();
end
end
endmodule