How the output is coming 5 at display?

SystemVerilog
1

module tb();
initial

            begin

               for(int i=0;i<5;i++)

                fork

                   $write(i);

                join_none

          #0 $display;

          end

endmodule

Allocation: Simulator allocated 5279 kB (elbread=1024 elab2=4104 kernel=150 sdf=0)

KERNEL: ASDB file was created in location /home/runner/dataset.asdb

run -all;

KERNEL: 5 5 5 5 5

KERNEL: Simulation has finished. There are no more test vectors to simulate.

exit

VSIM: Simulation has finished.

2

In reply to Dark_knight:

Please see: for loop inside fork join_none | Verification Academy

3

In reply to Dark_knight:

As Dave mentioned, use “automatic” variable inside for loop. A module is a static entity so it will require explicit automatic variable declaration.

module tb();
initial begin
  for(int i=0;i<5;i++) fork
    automatic int j=i;
    $write(j); // This will print 1 2 3 4 5
  join_none
  #0 $display;
end 
endmodule
4

Thank you Dave.

5

In reply to sharvil111:

thank you sharvil