Inside my testbench module, I wish to perform some conditional checks about whether or not certain parts of the circuit have been sensitized during the simulation process. The thing is, that for every logic simulation launched, I wish to probe different signals. The signals that are to be probed are exported from the bash script that invokes the logic simulator.
My question is, given a hierarchical circuit path such as: “tb_top.module_a.submodule_b.net1” how can I use it in e.g.,
if
statements in the context of systemVerilog?
For example
This happens in the bash script that invokes the simulator
// Inside the tb_top
import "DPI-C" function string get_env(input string env_name);
always_ff @(posedge clk, nenedge rst_n) begin
if (getenv("NET_A") == 1b'1) begin // read the env var and map it to a circuit net.
$display("Net has been sensitized!");
end
end
My question here is, what is the correct way of handling this situation?
Thank you in advance.
SystemVerilog has a C-based API (Verilog Procedural Interface VPI) that gives you access to a simulator’s database. There are routines like vpi_get_handle_by_name which gives you a handle to an signal looked up by a string name. And then you can use vpi_get_value the gives you the current value of that signal.
Use of the VPI needs quite a bit of additional knowledge and many simulators give you built-in routines to handle this common application without having to break into C code. In Modelsim/Questa, it is called Signal_Spy.
But regardless of whether you use the VPI or tool specific routines, looking up a signal by string name has severe performance implications because it prevents many optimizations. Unless a signal represents a storage element, it usually does not keep its value around for queries.
It would be much better to use the signal path name directly