How to make different binds of the same assertion module?

SystemVerilog
1

Hi,
I’m facing a problem in binding my assertion module to DUT.
Consider the below code.
module A #(Parameter X = 5, Parameter Y = 10) (
input a,
input b,
output c
);
.
.
.
endmodule

The above module A is my DUT. Let the assertion module name be AM.
The module A is instantiated in different hierarchies in the design. Parameter X value is not same in all the instances of the module A. So I have created different bind statements like shown below.

bind A AM #(.X(10)) bind_1(signals list);
bind A AM #(.X(20)) bind_2(signals list);

consider that bind_1 is happening at path_1 in my design and bind_2 is happening at path_2. What I’m seeing is, at path_1 both the binds bind_1 and bind_2 are being bound and same in path_2 both the binds are happening. I want bind_1 to be bound only in path_1 and bind_2 to be bound only to path_2. Is there is a way to do this in sv? please help me with this.

Thanks

2

In reply to Raj Guru:

There are several variations of the bind statement that allows you to target specific instances of a module instantiation:

To instantiate instantiated_module in all instances of target_module:
bind target_module instantiated_module instantiation_name(port_connections);

To instantiate instantiated_module in all instances of target_module with instance name of a1:
bind target_module:a1 instantiated_module instantiation_name(port_connections);

To instantiate instantiated_module in a hierarchical instance of target_module:
bind target_module:dut.sub_block.a1 instantiated_module instantiation_name(port_connections);

You likely want to use the third variation.

3

In reply to cgales:
Thanks for the help. The third variation worked.